1. Technical Field
The present disclosure relates to a receiving apparatus that binary discriminates differential signals having been differentially converted.
2. Description of the Related Art
A conventional digital binary signal receiving apparatus discriminates a signal, in synchronism with a clock signal, and determines for the signal a voltage level V0 corresponding to logical value 0 or a voltage level V1 corresponding to logical value 1. However, along with the increase of the speed of digital data transmission in recent years, there becomes apparent an issue that a discrimination timing is displaced due to skew of data between signals or that a quality of signal is deteriorated due to a differential signal skew between differential signals (the difference between arrival timings, from a transmitter to a receiver, of the positive signal and the negative signal). On the other hand, Japanese Patent No. 4,064,630 discloses a low voltage differential receiver that is equipped with a circuit for adjusting the skew between a data signal and a clock signal, for example. Further, Unexamined Japanese Patent Publication No. 2011-193039 discloses a receiving circuit in which an error rate with respect to a signal quality is reduced by an over-sampling technique that keeps the sampling number constant for one unit interval.